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[1]Z. Yan, C. Li*, J. Guo, and Y. Zhuang, “A GaAs Sb /In Ga0.47As heterojunction Z-gate TFET with hetero-gate-dielectric,” Superlattices and Microstructures, vol. 129, pp. 282–293, May 2019.
[2]Z. Yan, C. Li*, J. Guo, H. Jiang, J. Chen, and Y. Zhuang, “An Optimized GaAsSb/InGaAs Heterojunction L-shape Tunnel Field-Effect Transistor,” in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018, pp. 1–3.
[3]C. Li*, X. Zhao, Y. Zhuang, Z. Yan, J. Guo, and R. Han, “Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and Analog/RF performance enhancement,” Superlattices and Microstructures, vol. 115, pp. 154–167, Mar. 2018.
[4]C. Li*, Z.-R. Yan, Y.-Q. Zhuang, X.-L. Zhao, and J.-M. Guo, “Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric,” Chinese Phys. B, vol. 27, no. 7, pp. 78502–078502, 2018.
[5]J. Guo, C. Li*, Z. Yan, H. Jiang, J. Chen, and Y. Zhuang, “Influence of trap-assisted tunneling on Subthreshold Slope of Ge/Si heterojunction L-shaped TFETs,” in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018, pp. 1–3.
[6]Z. Jiang, Y. Zhuang, C. Li*, and P. Wang, “Tunnel Dielectric Field-Effect Transistors with High Peak-to-Valley Current Ratio,” Journal of Electronic Materials, vol. 46, no. 2, pp. 1088–1092, Feb. 2017.
[7]Z. Jiang, Y. Zhuang, C. Li*, P. Wang, and Y. Liu, “Impact of low/high-κ spacer–source overlap on characteristics of tunnel dielectric based tunnel field-effect transistor,” J. Cent. South Univ., vol. 24, no. 11, pp. 2572–2581, Nov. 2017.
[8]P. Wang, Y. Zhuang, C. Li*, Y. Liu, and Z. Jiang, “Potential-based threshold voltage and subthreshold swing models for junctionless double-gate metal-oxide-semiconductor field-effect transistor with dual-material gate,” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 29, no. 2, pp. 230–242, Mar. 2016.
[9]P. Wang, Y. Zhuang, C. Li*, Z. Jiang, and Y. Liu, “Drain current model for double-gate tunnel field-effect transistor with hetero-gate-dielectric and source-pocket,” Microelectronics Reliability, vol. 59, pp. 30–36, Apr. 2016.
[10]Z. Jiang, Y.-Q. Zhuang, C. Li*, P. Wang, and Y.-Q. Liu, “Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor,” Chinese Phys. B, vol. 25, no. 2, p. 027701, 2016.
[11]Z. Jiang et al., “Impact of Interface Traps on Direct and Alternating Current in Tunneling Field-Effect Transistors, Impact of Interface Traps on Direct and Alternating Current in Tunneling Field-Effect Transistors,” Journal of Electrical and Computer Engineering, Journal of Electrical and Computer Engineering, vol. 2015, 2015, p. e630178, Sep. 2015.
[12]Z. Jiang et al., “Drive Current Enhancement in TFET by Dual Source Region, Drive Current Enhancement in TFET by Dual Source Region,” Journal of Electrical and Computer Engineering, Journal of Electrical and Computer Engineering, vol. 2015, 2015, p. e905718, May 2015.
[13]L. Yu-An, Z. Yi-Qi, M. Xiao-Hua, D. Ming, B. Jun-Lin, and L. Cong, “A unified drain current 1/ f noise model for GaN-based high electron mobility transistors,” Chinese Phys. B, vol. 23, no. 2, p. 020701, 2014.
[14]P. Wang, Y. Zhuang, C. Li*, Y. Li, and Z. Jiang, “Subthreshold behavior models for nanoscale junctionless double-gate MOSFETs with dual-material gate stack,” Japanese Journal of Applied Physics, vol. 53, no. 8, p. 084201, Aug. 2014.
[15]P. Wang, Y. Zhuang, C. Li*, and Z. Jiang, “Analytical modeling for double-gate TFET with tri-material gate,” in 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014, pp. 1–3.
[16]L. Shi, Y. Zhuang, C. Li*, and D. Li, “Analytical modeling of the direct tunneling current through high- k gate stacks for long-channel cylindrical surrounding-gate MOSFETs,” J. Semicond., vol. 35, no. 3, p. 034009, 2014.
[17]Y. Liu, Y. Zhang, and C. Li, “Quantum percolation tunneling current 1/f,” Sci. China Phys. Mech. Astron., vol. 57, no. 9, pp. 1637–1643, Jul. 2014.
[18]C. Li*, Y. Zhuang, P. Wang, Z. Jiang, and L. Zhang, “A new analytical model for junctionless cylindrical surrounding-gate MOSFETs,” in 2014 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2014, pp. 1–2.
[19]C. Li*, Y. Zhuang, R. Han, and G. Jin, “Subthreshold behavior models for short-channel junctionless tri-material cylindrical surrounding-gate MOSFET,” Microelectronics Reliability, vol. 54, no. 6–7, pp. 1274–1281, Jun. 2014.
[20]C. Li*, Y.-Q. Zhuang, L. Zhang, and G. Jin, “Quasi-two-dimensional threshold voltage model for junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-material gate,” Chinese Phys. B, vol. 23, no. 1, p. 018501, 2014.
[21]C. Li*, Y.-Q. Zhuang, L. Zhang, and G. Jin, “A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs,” Chinese Phys. B, vol. 23, no. 3, p. 038502, 2014.
[22]Z. Jiang, Y. Zhuang, C. Li*, and W. Ping, “The hetero material gateand hetero-junction tunnel field-effect transistor with pocket,” in 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014, pp. 1–3.
[23]C. Li*, Y. Zhuang, S. Di, and R. Han, “Subthreshold Behavior Models for Nanoscale Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs,” IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3655–3662, Nov. 2013.
[24]C. Li*, Y. Zhuang, L. Zhang, and J. Bao, “Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric,” Chinese Phys. B, vol. 21, no. 4, p. 048501, 2012.
[25]C. Li*, Y.-Q. Zhuang, R. Han, L. Zhang, and J. Bao, “Analytical modeling of asymmetric HALO-doped surrounding-gate MOSFET with gate overlapped lightly-doped drain,” Acta Phys. Sin., vol. 61, no. 7, p. 078504, Apr. 2012.
[26]C. Li*, Y. Zhuang, and L. Zhang, “Simulation study on FinFET with tri-material gate,” in 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), 2012, pp. 1–3.
[27]C. Li*, Y. Zhuang, and R. Han, “New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs,” J. Semicond., vol. 32, no. 7, p. 074002, 2011.
[28]C. Li*, Y. Zhuang, and R. Han, “Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension,” Microelectronics Journal, vol. 42, no. 2, pp. 341–346, Feb. 2011.
[29]C. Li*, Y. Zhuang, R. Han, G. Jin, and J. Bao, “Analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions,” Microelectronics Reliability, vol. 51, no. 12, pp. 2053–2058, Dec. 2011.
[30]C. Li*, Y.-Q. Zhuang, and R. Han, “Analytical Threshold Model for Nanoscale Cylindrical Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistor with High-κ Gate Dielectric and Tri-Material Gate Stack,” Japanese Journal of Applied Physics, vol. 49, no. 12, p. 124202, Dec. 2010.