[1] 3-D Compact Marchand Balun Design Based on Through-Silicon via Technology for Monolithic and 3-D Integration. IEEE Trans. on Very Large Scale Integration(VLSI) Systems. 2022.30(8):1107-1118.

[2]Optimization and Analysis of Microchannels Under Complex Power Distribution in 3-D ICs. IEEE Trans. on Components, Packaging and Manufacturing Technology.2022.13(3):537-543.

[3]Time-Domain Power Distribution Network (PDN) Analysis for 3-D Integrated Circuits Based on WLP-FDTD. IEEE Trans. on Components, Packaging and Manufacturing Technology.2022.13(3):551-561.

[4]A TSV-Based 3-D Electromagnetic Bandgap Structure on an Interposer for Noise Suppression. IEEE Trans. on Components, Packaging and Manufacturing Technology.2021.12(1):147-154.

[5]Compact and Physics-Based Modeling of 3-D Inductor Based on Through Silicon Via. IEEE Electron Device Letters. 2021.42(10):1559-1562.

[6]Model for Rapidly Computing the Highest Temperature Based on Fermat Point in Chips AIAA Journal of Thermophysics and Heat Transfer.2021.35(1):92-97.

[7]MTL-based modeling and analysis of the effects of TSV noise coupling on the power delivery networks in 3D ICs. Journal of Computatinal Electronics(2020) 19:543-554.

[8] Thermal-Aware Modelling and Analysis for a Power Distribution Network Including Through Silicon Vias in 3-D ICs. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems. 2019. 38(7):1278-1290.

[9]An Effective Approach for Thermal Performance Analysis of Three-Dimensional Integrated Circuits with Through-Silicon Vias.. IEEE Trans. on Components, Packaging and Manufacturing Technology.2019.9(5):877-887.

[10]Nonlinear Electrothermal Model for Investigating Transient Temperature Response of a Through-Silicon Via Array Applied With Gaussian Pulses in 3-D IC. IEEE Trans on Electron Devices. 2019.66(2):1032-1040

[11]Power and Thermal Constraints-Driven Modeling and Optimization for Through Silicon Via-Based Power Distribution Network. ASME Trans. Journal of Electronic Packaging. 2018.140(4):041002-1.

[12]Accurate Inductance Modeling of 3-D Inductor based on TSV IEEE Microwave and Wireless Components Letters.2018.28(10):900-902.

[13]Analysis of the Coupling Capacitance Between TSVs and Adjacent RDL Interconnections. IEEE Trans. on Electromagnetic Compatibility.2019.61(2): 512-520.

[14]A Simplified Closed-form Model and Analysis for Coaxial-annular through-silicon via in 3-D ICs. IEEE Trans. on Components, Packaging and Manufacturing Technology.2018. 8(9):1650-1657.

[15]Universal Closed-form expression based on magnetic flux density for the inductance of Tapered Through-Silicon Vias(T-TSVs), Microelectronics Journal.2017.63(1):20-26.